The present invention relates to a metal-oxide semiconductor (MOS) transistor, and more particularly, to a high-voltage transistor which can reduce layout space and provide improved characteristics thereof, and a manufacturing method therefor.
With increased integration of semiconductor devices, the channel length of a MOS transistor becomes shorter. Thus, short-channel effects such as reduced threshold voltage, deteriorated sub-threshold characteristics and reduced source-drain breakdown voltage have been a serious impediment to the high-integration of semiconductor devices. Therefore, research into new structures for remedying these short-channel effects is under progress. Particularly, structures have been developed which increase the breakdown voltage of a MOS transistor.
FIG. 1 is a cross-sectional view of a transistor having a high breakdown voltage, which is disclosed in U.S. Pat. No. 4,172,260.
Referring to FIG. 1, a first oxide film (not shown) is formed on a P-type semiconductor substrate 1 by a thermal oxidation. After selectively etching the first oxide film, an N.sup.+ -type impurity is diffused into the substrate 1 to form an N.sup.+ -type source region 7 and drain region 6. The first oxide film is removed and a thermal oxidizing process is conducted to form a second oxide film 2 on the substrate 1. After depositing a polycrystalline silicon (polysilicon) on the second oxide film 2, the polysilicon layer is patterned by a photolithographic etching process to form a gate electrode 3. Then, using gate electrode 3 as a mask, N.sup.- -type impurity ions are implanted to form an N.sup.- -type register region 8. At this time, the dose of the N.sup.- -type impurity is an important parameter to determine the breakdown voltage. A third oxide film (not shown) which extends from on the gate electrode 3 toward the drain region 6 and which terminates at an intermediate position of the resistor region 8 is formed. Using the gate electrode 3 and the third oxide film as a mask, N-type impurity ions are implanted to form an N-type intermediate region 5. Thus, the register region 8 is segmented into N.sup.- -type region 4 and N-type intermediate region 5. Subsequently, after removing the third oxide film, a passivation film (not shown) is formed on the resultant structure, and a contact process for exposing the source region 7 and drain region 6 is conducted.
According to the aforementioned conventional method, since the width of a depletion layer formed near the drain region is made large by forming N.sup.- - and N-type regions between the N.sup.+ -drain region of a transistor and gate electrode 3, the electrical field applied to the drain region is reduced. As a result, however, the layout space is increased by as much as the offset length corresponding to the N.sup.- - and N-type regions, which is disadvantageous for high-integration.
Meanwhile, a method for obtaining a high breakdown voltage without increasing layout space is disclosed in U.S. Pat. No. 4,950,617. In this method, an electric field is reduced by manufacturing a transistor having a doubly diffused drain (DDD) structure, as shown in FIG. 2.
Referring to FIG. 2, a gate insulation film 11 is formed on a P-type semiconductor substrate 10 by a thermal oxidizing process. Subsequently, polysilicon is deposited thereon and patterned by a photolithographic etching process to form a gate electrode 12. Using the gate electrode 12 as a mask, N.sup.- -type impurity ions are implanted. Next, N.sup.- source and drain regions 14 and 14' in which a deep junction is diffused are formed by conducting a thermal treatment at a high temperature for a long time. Using the gate electrode 12 again as a mask, N.sup.+ -impurity ions are again implanted, thereby forming N.sup.+ source and drain regions 13 and 13'.
According to the conventional method having the aforementioned DDD transistor, a high-temperature and long-duration thermal treatment is necessary for forming a deep junction of the regions 14 and 14', which results in lowered transistor performance and short-channel effects. Therefore, in order to solve the problem, the channel length of the transistor should be increased, which makes it difficult to adopt the method shown in FIG. 2 for a highly integrated semiconductor device.